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HS-6664RH-T
Data Sheet July 1999 File Number
4609.1
Radiation Hardened 8K x 8 CMOS PROM
Intersil's Satellite Applications FlowTM (SAF) devices are fully tested and guaranteed to 100kRAD total dose. These QML Class T devices are processed to a standard flow intended to meet the cost and shorter lead-time needs of large volume satellite manufacturers, while maintaining a high level of reliability. The Intersil HS-6664RH-T is a radiation hardened 64K CMOS PROM, organized in an 8K word by 8-bit format. The chip is manufactured using a radiation hardened CMOS process, and utilizes synchronous circuit design techniques to achieve high speed performance with very low power dissipation. On-chip address latches are provided, allowing easy interfacing with microprocessors that use a multiplexed address/data bus structure. The output enable control (G) simplifies system interfacing by allowing output data bus control in addition to the chip enable control (E). All bits are manufactured storing a logical "0" and can be selectively programmed for a logical "1" at any bit location.
Features
* QML Class T, Per MIL-PRF-38535 * Radiation Performance - Gamma Dose () 1 x 105 RAD(Si) - No Latch-Up, SEU LET >100MeV/mg/cm2 * Transient Output Upset >5 x 108 RAD (Si)/s * Fast Access Time - 35ns (Typical) * Single 5V Power Supply, Synchronous Operation * Single Pulse 10V Field Programmable NiCr Fuses * On-Chip Address Latches, Three-State Outputs * Low Standby Current <500A (Pre-Rad) * Low Operating Current <15mA/MHz
Pinouts
HS1-6664RH-T (SBDIP), CDIP2-T28 TOP VIEW
NC 1 A12 2 A7 3 A6 4 A5 5 A4 6 A3 7 A2 8 28 VDD 27 P 26 NC 25 A8 24 A9 23 A11 22 G 21 A10 20 E 19 DQ7 18 DQ6 17 DQ5 16 DQ4 15 DQ3
Specifications
Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed below must be used when ordering. Detailed Electrical Specifications for the HS-666s4RH-T are contained in SMD 5962-95626. A "hot-link" is provided from our website for downloading. www.intersil.com/spacedefense/newsafclasst.asp Intersil's Quality Management Plan (QM Plan), listing all Class T screening operations, is also available on our website. www.intersil.com/quality/manuals.asp
A1 9 A0 10 DQ0 11 DQ1 12 DQ2 13 GND 14
HS9-6664RH-T (FLATPACK), CDFP3-F28 TOP VIEW
NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD P NC A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
Ordering Information
ORDERING INFORMATION 5962R9562601TXC HS1-6664RH/Proto 5962R9562601TYC HS9-6664RH/Proto PART NUMBER HS1-6664RH-T HS1-6664RH/Proto HS9-6664RH-T HS9-6664RH/Proto TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125
A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND
NOTE: Minimum order quantity for -T is 150 units through
distribution, or 450 units direct.
P must be hardwired at all times to VDD, except during programming.
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999 Satellite Applications FlowTM (SAF) is a trademark of Intersil Corporation.
HS-6664RH-T Functional Diagram
MSB A2 A3 A4 A5 A6 A7 A8 LSB A LATCHED ADDRESS REGISTER 8 A 8 E E 32 32 32 32 32 32 32 32 GATED ROW DECODER 256 256 X 256 MATRIX
1 OF 8
P
8 E E A G E 5
GATED COLUMN DECODER PROGRAMMING, AND DATA OUTPUT CONTROL A 5
8
Q0 - Q7
LATCHED ADDRESS REGISTER
P must be hardwired at all times to VDD, except during programming.
MSB A0 A1 A10 A9 A11 A12 LSB
TRUTH TABLE E 0 0 1 G 0 1 X MODE Enabled Output Disabled Disabled
Timing Waveform
TAVQV 3.0V 1.5V 1.5V VALID ADDRESS ADDRESSES TELEL TAVEL TELAX TELEH 3.0V 1.5V E TEHEL G 1.5V TGLQX TELQX VALID DATA TS TELQV TGLQV 1.5V 0V TGHQZ TEHQZ 3.0V 1.5V 1.5V 1.5V 0V VALID ADDRESSES 0V
DATA OUTPUT Q0 - Q7
FIGURE 1. READ CYCLE
2
HS-6664RH-T Die Characteristics
DIE DIMENSIONS: (6883m x 7798m x 483m 25.4m) 271 x 307 x 19mils 1mil METALLIZATION: PASSIVATION: Type: Silox (SiO2) Thickness: 8kA 1kA WORST CASE CURRENT DENSITY: < 2.0e5 A/cm2 TRANSISTOR COUNT: 110, 874, (27,719 Gates) PROCESS: AVLSI
Si/AI/Cu 2kA 500A TiW M2: 10kA 2kA Si/AI/Cu
SUBSTRATE POTENTIAL: VDD BACKSIDE FINISH: Silicon
MI: 6kA 1kA
Metallization Mask Layout
HS-6664RH-T
(28) VDD (2) A12 (23) A11 (26) NC (25) A8 (24) A9 (7) A3 (6) A4 (5) A5 (4) A6 (3) A7 (27) P (22) G A10 (21)
VSS
A0 (10)
E (20)
VDD
VSS VDD
A2 (8)
A1 (9)
GND (14)
DQ0 (11)
DQ1 (12)
DQ2 (13)
DQ3 (15)
DQ4 (16)
DQ5 (17)
DQ6 (18)
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
3
DQ7 (19)

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